FIG. 3 is a schematic diagram showing a conventional dual port DRAM. As shown in the drawing, a RAM section 1 for reading and writing data at random is connected to a SAM section 3 through transfer gates 2. A control signal CS is inputted to a control circuit 7. A transfer signal TS is inputted from the control circuit 7 to the transfer gates 2. In response to a signal S from the control circuit 7 and on the basis of an address A, an address select signal ASS for designating a row address to be accessed is given from an address decoder 7a to the RAM section 1. External input data ED inputted through a data buffer 5 is written in an area on the SAM section 3, which is designated by a serial address pointer 4. An address AD and an external clock SC are applied to a serial address decoder 6. The serial address decoder 6 decodes the applied address AD and gives a serial decoded address signal SAS to the serial address pointer 4 to acquire the external input data ED by the SAM section 3 in response to the external clock SC. Further, in response to the external clock SC, a counter of the SAM section 3 is incremented.
The operation of the conventional dual port DRAM will be described hereinbelow.
The external input data ED to be written in the RAM section 1 is given to the data buffer 5. This external input data ED is first stored in the SAM section 3. That is, on the basis of the address AD given to the address decoder 6, the serial address signal SAS is inputted to the serial address pointer 4 as a start address. Thereafter, in response to the external clock SC, the external input data ED is acquired by the SAM section 3 and further the counter of the SAM section 3 is incremented. Successively, on the basis of the transfer signal TS applied from the control circuit 7 to which the control signal CS is given, the transfer gates 2 are opened. Accordingly, all the data on the SAM section 3 are transferred in parallel to each other to a row address on the RAM section 1 designated by the address select signal ASS given by the address decoder 7a.
As described above, the conventional dual port DRAM is so configured that all the data of the SAM section 3 are transferred to a row address of the RAM section 1 together. Therefore, although data can be transferred in one input or output unit, it is impossible to transfer data partially. In more detail, as shown in FIG. 4, it is impossible to rewrite only data in the area B of a rewritable region 13 in one row region 14 in the RAM section 1. In other words, it is impossible to rewrite only the data in the area A of the SAM section 3 and further transfer the rewritten data to the RAM section 1 for a rewriting operation. If the data rewriting operation is executed, the data in the areas A1 and A2 other than the area A of the SAM section 3 are transferred to the row region 14 of the RAM section 1 through the transfer gates 2, with the result that the data (not required to be rewritten) in the areas C and D other than the area B are destroyed.
Consequently, in the conventional dual port DRAM, even when a partial area in a row of the RAM section 1 is required to be rewritten, after the data in all the areas A1, A and A2 of the SAM section 3 have been all once rewritten, the rewritten data must be transferred to the RAM section 1. Alternatively, after the data in a row address including an area required to be written have been all once transferred from the RAM section 1 to the SAM section 3, only data in the necessary area must be rewritten in the SAM section 3 and further must be returned to the RAM section 1.
To overcome the above-mentioned disadvantage, there has been so far known a block write function for each 4-cell unit or a flash write function for row unit. In these methods, however, there exists a problem in that the bits to be written are not redundant and therefore it is impossible to freely select the data areas.
In particular, in the case where multiple windows are displayed on a CRT display picture with the use of a semiconductor memory device, even when only one image is required to be written, it is necessary to check and further input data for the other images not required to be rewritten, with the result that a long data processing time is inevitably needed and therefore the display image cannot be switched smoothly under preferable conditions.
As described above, in the conventional semiconductor memory device, when a partial area of the RAM section is required to be rewritten, unnecessary processing cycles to be executed. Therefore, there exists problems in that a long processing time is required for a partial rewriting operation and further the peripheral circuits become complicated, as compared with the whole row data rewriting operation in the RAM section.